The LoRa modulation itself is a PHY that can be used in all network topologies. A mesh network extends the range of the network but comes at the cost of reduced network capacity, synchronization overhead, and reduced battery lifetime due to synchronization and hops. With the increased link budget and range capability of LoRa, there is no need for a mesh network architecture to extend the range so a star architecture was chosen for LoRaWAN to optimize the network capacity, battery lifetime, and easy installation. 

The SX127x LoRa device has a FIFO of 256bytes in LoRa mode. In theory, all the 256Bytes can be used for TX or RX. However, with a low data-rate configuration, the time on air with a 256byte payload will be very long (several seconds or even longer), which is not good for resisting fading and high interference environments. This is not a robust configuration in most environments so it is suggested that if a long payload is desired with a low data-rate then the packet be split into a few shorter packets. 

Follow the steps (I – V) listed below:

The RegPktRssiValue and RegRssiValue are both useful in LoRa mode. RegPktRssiValue refers to the packet RSSI level, and the RegRssiValue is similar to the RSSI that can be found in (non LoRa) FSK mode. As you know, LoRa can demodulate the packet below the noise floor (PktRssi result) then CurrentRssi will then be equal to or more than the noise floor.

For more details about how to calculate these two RSSI Values, please refer to the Semtech API or latest LoRa datasheets. 

When you start your design, check the DIO Mapping in both the LoRa mode and FSK mode. You can find the DIO Mapping information in SX127x LoRa® datasheets. The DIOs do not function as normal (typical) MCU GPIOs. There are some special interrupt signals (or clock outputs) to indicate the event or status of the chipset, which then make your FW design easier to implement. In theory, you could connect no DIOs and then poll the related register to know the status result. However, we suggest that you connect the DIO as much as possible for external interrupt functionality which saves on the resource loading of the MCU and permits a very low-power operation mode (the MCU can sleep while packet it Tx’ed or Rx’ed). 

No, the maximum packet length is 256 bytes in LoRa mode

In LoRa mode, even if the CRC is wrong the payload will be filled into the FIFO. Bit PayloadCrcError must be checked before fetching the payload to know its integrity. In Explicit Header mode, there is a small probability that a false detection creates a “ghost” packet. Either the false header has CrcOn bit turned on, and then the payload will be wrong, and the modem will flag it as a PayloadCrcError condition, so packet can easily be filtered out. Or the false header has CrcOn disabled, in which case the mode will consider the packet as a good one. These infrequent bad packet will have a random length (extracted from the false header info), and can be easily filtered by the host, for instance by seeing that their size is unexpected.

First of all, check the frequency offset caused by the crystal between the two devices. The BW, center frequency, and data rate are all derived from the crystal frequency.

Second, check the software/firmware settings on both sides for frequency, bandwidth, spreading factor, coding rate and packet structure to ensure they are the same. 

If it is just for measurement, you can use the Frequency synthesis TX (FSTX) mode as listed in the LoRa register table to generate a CW tone based on the LoRa configuration.

Normally, a +/-10ppm XTAL is good enough for most designs with a bandwidth of 62.5kHz or higher. For bandwidth (BW) less than 62.5kHz, a TCXO is strongly suggested. For more details about the specification of the crystal, please refer to the datasheet and LoRa Modem Calculator tool and application note AN1200.14_XO_Guidance_LoRa_Modulation_STD”. 

Three parameters are important to test in mass production: frequency tolerance, output power, and sensitivity. The frequency and output power are easy to test with a spectrum analyzer. If your signal generator cannot generate a LoRa signal, testing the sensitivity with FSK mode is strongly suggested.

There is only one RF chain in the chip, and the FSK and LoRa demodulation is done in the digital domain. The RF path could potentially be misassembled (ex: dry joint on a DC-cut) so this is important to verify.

The digital portion of the chip where the LoRa and FSK modulation is done is isolated from the effects of assembly so testing FSK sensitivity is sufficient for verifying the production test performance. The digital and LoRa modulation are tested extensively in the chip production test. 

1. Please make sure that you connect the right pin (PA_Boost) set for 20dBm output. There are two output ports for each band. One is high power port called PA_boost, another is high efficiency port called RFO.
2. Then, check the configuration in SW. Three registers should be configured correctly: RegPaConfig, RegOcp and RegPaDac. This means that you should select the right pin for proper output in SW, then set the right value refer to power level you need.
3.  Confirm they match per the Semtech reference design to make a good layout. This is important to achieve the maximum output power possible.

Yes, it is no problem. The LoRa device can be switched from FSK to LoRa (and vice versa) via simple SPI register write. This has no effect on the performance or reliability of the device. A LoRa device can be configured and reconfigured to any of the parameters as specified in the datasheets. 

The +20dBm specification is for the output power at the pin of the chip. The band-pass filter and RF switch have insertion loss characteristics as in any RF system. Achieving +19dBm at the antenna is typical performance after matching and filtering. 

Instead of using a Received Signal Strength Indicator (RSSI) method to identify if a signal is present, the CAD is used to detect the presence of a LoRa signal. It has the capability to differentiate between noise and a desired LoRa signal. The CAD process requires two symbols, and if the CAD is detected, the CAD_Detected interrupt will be asserted and the device will stay in RX mode to receive the data payload.

With a LoRa device (ex: SX1272 or SX1276), a lower cost crystal can be used. In narrow band technology, an expensive temperature controlled crystal oscillator is needed to minimize frequency drift during RX/TX. A typical bill of materials cost for a complete end-node is $2-$5 depending on volume and features. A long transmit range means simpler network infrastructure and lower cost of deployment as no repeaters are necessary. Lower power consumption means use lower cost batteries and network maintenance. 

At the chip pin, the output power is +20dBm and at the antenna after matching/filtering loss, the power is +19dBm +/-0.5dB. Different regions have different regulations for max output power, and the LoRaWAN specification defines different output power for the different regions to maximize the link budget. 

LoRaWAN defines a specific set of data rates, but the LoRa chip or PHY is capable of more options. The SX1272 supports data rates from 0.3 to 37.5kbps and the SX1276 0.018 to 37.5kbps.

The LoRa modem is capable of co-channel GMSK rejection of up to 19.5 dB or stated differently, it can receive signals 19.5dB below an interfering signal or the noise floor. This immunity to interference permits the simple coexistence of LoRa modulated systems either in bands of heavy spectral usage or in hybrid communication networks that use LoRa to extend range when legacy modulation schemes fail. 

The term gateway and concentrator are both used, but they are equivalent components in a LoRa system. In other industries, the definition of gateway and concentrator imply different components.